Our product line includes best in class IP and Design Services for ASIC and FPGA

  • PLL and OSC from 180nm to 7nm
  • LC PLL , Ring Oscillator PLL, Customized PLL
  • Ultra Low Jitter/Power/Area
  • Core voltage or IO voltage
  • Spread Spectrum
  • From 180nm to 28nm, 100Mbps to 20Gps
  • Multi-protocol PMA up to 12.7G, DFE, Eye-Monitor
  • Embedded in Microsemi's 28nm PolarFire FPGAs
  • Random jitter < 1 ps RMS using XTL clock
  • Standards including SGMII, XAUI, JESD204B, OIF-CEI, V-by-1, CameraLink, FastLVDS, CPRI and semi-custom 
   Other IPs
  • Free running OSC (no external components) <30uW
  • Digital Dual-Loop PLL
  • Bi-directional LVDS >1.25Gbps .....2.5Gpbs in FinFET
  • Bandgap, POR
  • Clocking Library - CML buffers & CML Mux
   SAR ADCs and DACs
  • Ultra High-Speed and High-Performance
  • Off-the-shelf and customized
  • 7 bit to 12 bit
  • 20 Msps to 5 Gsps
  • From 180 to 14nm
   IP, UVC/UVM VIP, VITAL models
  • SOC Design/Verification Services for ASIC &FPGA
  • 200 engineers in 3 design centers (Serbia, Greece)
  • ISO 9001 (quality) and ISO 27001 (security) certified
  • ARM Approved Design Partner (1 of 7 Worldwide)
  • Soft IP lib. MIPI, JESD204B, I2S, SPI Flash Memory Controller, Serial RapidIO
   DDR/LPDDR IP, VIP, Design services
  • DDR3/4, LPDDR3/4 Controllers and VIP  
  • 10G Ethernet switch
  • For ASIC and FPGA implementation
  • FPGA Prototyping
   DDR/LPDDR IP, Design & Manufacturing services
  • SOC Design, Integration and Manufactoring  
  • TSMC, UMC, Samsung, GF, SMIC
  • Complete (LP)DDR Memory Subsystem IP
  • LCD Driver IC
  • LCD Timing Controllers (TCON) ICs
  • LTE Uplink Controller IC
  • DSL Booster and Noice Canceller IC
  Communication IP and Design Services
  • Wireless, Wireline, Automotive, Aerospace  
  • For ASIC and FPGA implementation
  • CPRI, Ethernet, FFT/IFFT, JESD204x
  • Radio Over Ethernet
  • Services related to Digital Communication:
    • ‚ÄčAnalysis and spec
    • Design and Implementation
    • Verification and Test
    • Documentation
   Video Compression and Image Processing
  • For ASIC and FPGA implementation
  • DisplayPort 1.4 Controllers (TX, RX)
  • DSC 1.2 Encoder/Decoder
  • H.264, MPEG-2, DV Video Decoders
  • Content Adaptive Deinterlacer
  • Image Scaler (Anisotropic)
  • Development Platform (on FPGA)