Our product line includes best in class IP and Design Services for ASIC and FPGA
PLL and OSC from 180nm to 3nm
LC PLL , Ring Oscillator PLL, Customized PLL
Ultra Low Jitter/Power/Area
Core voltage or IO voltage
Multiprotocol PMA and Protocol Specific PHYs
From 180nm to 16/12nm, 100Mbps up to 25Gbps
MPPMA Supports >30 protocols inc. PCIe Gen 1/2/3/4
Targeted PHYs for SGMII, 10G-KR, (e)DP and more
ISO 26262 compliant and AEC-Q100 qualified
TSMC partenr of the year 2017-2021 for AMS IP
Free running OSC (no external components) <30uW
Digital Dual-Loop PLL
Bi-directional LVDS >1.25Gbps .....2.5Gpbs in FinFET
Clocking Library - CML buffers & CML Mux
Comprehensive Design and Verification IP Solutions
Design IP - Broad Protocol Support
DDR, Ethernet, Serial Bus, Audio/Video, MIPI, Automotive, Bridge, DMA, Flash and High Speed Interfaces
Can be rapidly customized on-demand
Verification IP - Design to Silicon
Simulation, Emulation, Formal, Post Silicon, Memory Models
On-demans services for verification projects
On-chip protection for ESD/EOS/Latch-Up/EMC
TakeCharge® includes on-chip ESD (electrostatic discharge) and EOS (electrical overstress) protection devices for low voltage CMOS from 0.25um down to 7nm. Typical I/O application uses are: high-speed, low-leakage, low-capacitance, low-noise, RF, analog, over- and undervoltage tolerance; often combined with beyond standard robustness requirements.
PowerQubic® provides on-chip ESD and EOS protection devices for high voltage CMOS/BCD, typically 0.35um down to 0.18um and 5V to 50V. Typical I/O application uses are: automotive, industrial; mostly requiring high robustness for a combination of harsh ESD, EOS, LU (latch-up) and EMI (electromagnetic interference) specs.
PhyStar® groups Sofics’ robust circuit and interface solutions, including custom analog I/O’s, circuits that handle transient disturbances e.g. to provide antenna clipping or POR (power-on-reset), as well as automotive standard PHYs (e.g. a full LIN PHY with integrated ESD, EOS and EMC robustness).
Memory subsystem and AI platform IP
ORBITTM Memory Controller IP, OMCTM saves on area and power while offering >90% DRAM utilization using a proprietary out-of-order scheduling algorithm. It supports HBM3, GDDR6, LPDDR5/4, and DDR4/3/LPDDR4/3.
ORBITTM Network-on-Chip (NoC) Bus Interconnect IP, OICTM enables exceptional bus performance and flexible SoC design via automated end-to-end interconnect generation flow.
ORBITTM DDR PHY IP, OPHYTM is a high-speed Memory PHY IP optimized for applications such as AI/ML, HPC, mobile and automotive. It is fabricated using 12nm and 14nm technology, supporting GDDR6, LPDDR5/4 with more advanced nodes in the works.
ENLIGHTTM Neural Processor Unit (NPU) IP performs various operations of deep neural networks such as convolution, pooling, and non-linear activation functions for the edge computing environments while achieving an excellent PPA score.