Our product line includes best in class IP and Design Services for SoC design.

   Award Winning Analog Mixed Signal IP
  • Ring PLLs
  • LC PLLs
  • Oscillators
  • LVDS
  • Analog Glue
  • TSMC OIP partner of the year award 2017-2023
  • Global footprint
  Proffessional Layout Design Partner
  • TSMC Design Center Alians partner since 2022
  • Specializes in 3/5/7/12/16nm full custom layout
  • 230+ Layout engineers
  • 200+ Worldwide customers
  • Global footprint

  Formal Verification Services
  • In the Setup stage, high-risk blocks are identified, verification targets are defined and KPIs are established.
  • During Execution, the team submits feedback and on-the-spot bug reports.
  • Delivery is a verification IP (VIP) that accelerates runtime and integrates with existing regression tests.
  Comprehensive Design and Verification IP 
   Design IP
- Broad Protocol Support
  • DDR, Ethernet, Serial Bus, Audio/Video, MIPI, Automotive, DMA, Flash and High Speed Interfaces
  • Can be rapidly customized on-demand

‚Äč    Verification IP - Design to Silicon 

  • Simulation,Emulation, Post Silicon, Memory Models
  • On-demans services for verification projects 
  On-chip ESD protections, Analog & Digital IO
  • TakeCharge® Analog I/Os and on-chip ESD protection for low voltage CMOS.
  • PowerQubic® on-chip ESD and EOS protection devices for high voltage CMOS/BCD processes.
  • PhyStar®  Robust Circuit and Interface solutions. 
  Memory subsystem and AI platform IP
  • ORBITTM Memory Controller IP, OMCTM Delivers excellent performance achieved by its proprietary out-of-scheduling algorithm and high-speed implementation.
  • ORBITTM Network-on-Chip (NoC) Bus Interconnect IP, OICTM enables exceptional bus performance and flexible SoC design via automated end-to-end interconnect generation flow.
  • ORBITTM DDR PHY IP, OPHYTM features a state-of-the-art mixed-signal architecture that addresses the challenges of DRAM integration in high-performance and lower-power environments.