Our product line includes best in class IP and Design Services for ASIC and FPGA

   PLL 
  • PLL and OSC from 180nm to 7nm
  • LC PLL , Ring Oscillator PLL, Customized PLL
  • Ultra Low Jitter/Power/Area
  • Core voltage or IO voltage
  • Spread Spectrum
‚Äč    Multiprotocol PMA and Protocol Specific PHYs
  • From 180nm to 12nm, 100Mbps up to 25Gbps
  • MPPMA Supports >30 protocols inc. PCIe Gen 1/2/3/4
  • Targeted PHys for SGMII, Infiniband, V-by-1 and more
  • ISO 26262 compliant and AEC-Q100 qualified
  • TSMC partenr of the year 2018, 2017 for AMS-IP
   Other IPs
  • Free running OSC (no external components) <30uW
  • Digital Dual-Loop PLL
  • Bi-directional LVDS >1.25Gbps .....2.5Gpbs in FinFET
  • Bandgap, POR
  • Clocking Library - CML buffers & CML Mux
   SAR ADCs and DACs
  • Ultra High-Speed and High-Performance
  • Off-the-shelf and customized
  • 7 bit to 12 bit
  • 20 Msps to 5 Gsps
  • From 180 to 14nm
  • TSMC, UMC, GF, XFAB
   Complete SOC design and verification services
  • SOC Design/Verification Services for ASIC &FPGA
  • 200 engineers in 3 design centers (Serbia, Greece)
  • ISO 9001 (quality) and ISO 27001 (security) certified
  • ARM Approved Design Partner (1 of only a few WW)
  • Soft IP Core development V-by-1, HDMI, MIPI, UniPro
  • Reusable IoT platform using ARM IP package
  On-chip protection for ESD/EOS/Latch-Up/EMC
 
  • TakeCharge® includes on-chip ESD (electrostatic discharge) and EOS (electrical overstress) protection devices for low voltage CMOS from 0.25um down to 7nm. Typical I/O application uses are: high-speed, low-leakage, low-capacitance, low-noise, RF, analog, over- and undervoltage tolerance; often combined with beyond standard robustness requirements.
 
  • PowerQubic® provides on-chip ESD and EOS protection devices for high voltage CMOS/BCD, typically 0.35um down to 0.18um and 5V to 50V. Typical I/O application uses are: automotive, industrial; mostly requiring high robustness for a combination of harsh ESD, EOS, LU (latch-up) and EMI (electromagnetic interference) specs.
 
  • PhyStar®  groups Sofics’ robust circuit and interface solutions, including custom analog I/O’s, circuits that handle transient disturbances e.g. to provide antenna clipping or POR (power-on-reset), as well as automotive standard PHYs (e.g. a full LIN PHY with integrated ESD, EOS and EMC robustness).
   DDR/LPDDR IP, VIP, Design services
  • DDR3/4, LPDDR3/4 Controllers and VIP  
  • 10G Ethernet switch
  • For ASIC and FPGA implementation
  • IoT Platform
  • High Speed Serial Data Generator (FPGA borad)
  Communication IP and Design Services
  • Wireless, Wireline, Automotive, Aerospace  
  • For ASIC and FPGA implementation
  • CPRI, 25G Ethernet MAC/PCS, FFT/IFFT, JESD204C/B
  • Radio Over Ethernet
  • Services related to Digital Communication:
    • ‚ÄčAnalysis and spec
    • Design and Implementation
    • Verification and Test
    • Documentation