Our product line includes best in class IP and Design Services for ASIC and FPGA

  • PLL and OSC from 180nm to 3nm
  • LC PLL , Ring Oscillator PLL, Customized PLL
  • Ultra Low Jitter/Power/Area
  • Core voltage or IO voltage
  • Spread Spectrum
​    Multiprotocol PMA and Protocol Specific PHYs
  • From 180nm to 16/12nm, 100Mbps up to 25Gbps
  • MPPMA Supports >30 protocols inc. PCIe Gen 1/2/3/4
  • Targeted PHYs for SGMII, 10G-KR, (e)DP and more
  • ISO 26262 compliant and AEC-Q100 qualified
  • TSMC partenr of the year 2017-2020 for AMS IP
   Other IPs
  • Free running OSC (no external components) <30uW
  • Digital Dual-Loop PLL
  • Bi-directional LVDS >1.25Gbps .....2.5Gpbs in FinFET
  • Bandgap, POR
  • Clocking Library - CML buffers & CML Mux

   Interlaken ILA/ILK
  • Complete MAC/PCS
  • 1 to 32 Lanes, Lane rate up to 112Gbps
  • Low latency, low gate count and fully parametrized
  • Targeting both ASIC and FPGA in nodes down to 5nm
​    Ethernet 
  • Complete MAC/PCS/FEC
  • Single RTL code supports speeds from 1 to 800Gbps 
  • Low latency, low gate count and fully parametrized
  • Targeting both ASIC and FPGA in nodes down to 5nm
   Complete SOC design and verification services
  • SOC Design/Verification Services for ASIC &FPGA
  • 200 engineers in 3 design centers (Serbia, Greece)
  • ISO 9001 (quality) and ISO 27001 (security) certified
  • ARM Approved Design Partner
  • Soft IP Core development V-by-1, HDMI, MIPI, UniPro
  • Reusable IoT platform using ARM IP package
  On-chip protection for ESD/EOS/Latch-Up/EMC
  • TakeCharge® includes on-chip ESD (electrostatic discharge) and EOS (electrical overstress) protection devices for low voltage CMOS from 0.25um down to 7nm. Typical I/O application uses are: high-speed, low-leakage, low-capacitance, low-noise, RF, analog, over- and undervoltage tolerance; often combined with beyond standard robustness requirements.
  • PowerQubic® provides on-chip ESD and EOS protection devices for high voltage CMOS/BCD, typically 0.35um down to 0.18um and 5V to 50V. Typical I/O application uses are: automotive, industrial; mostly requiring high robustness for a combination of harsh ESD, EOS, LU (latch-up) and EMI (electromagnetic interference) specs.
  • PhyStar®  groups Sofics’ robust circuit and interface solutions, including custom analog I/O’s, circuits that handle transient disturbances e.g. to provide antenna clipping or POR (power-on-reset), as well as automotive standard PHYs (e.g. a full LIN PHY with integrated ESD, EOS and EMC robustness).
  Communication IP and Design Services
  • Wireless, Industrial, Automotive, Aerospace  
  • IP cores For ASIC and FPGA implementation
  • 25G Ethernet TSN MAC/PCS/Switch, JESD204C/B
  • Services related to Digital Communication:
    • ​Analysis and spec
    • Design and Implementation
    • Verification and Test
    • Documentation